1. Field of the Invention
The present invention relates to a memory system, a method for controlling the same, and an information processing device, and in particular, to a memory system accessed by a plurality of processors, a method for controlling the same, and an information processing device using the same.
2. Description of the Related Art
Recently, information processing devices assign particular types of calculations to dedicated processors other than a CPU (Central Processing Unit), such as GPU (Graphics Processing Unit) responsible for image processing and a codec (Coder/Decoder) responsible for data compression and expansion of audio and image data. This way, information processing can be accelerated.
FIG. 11 shows an example of a configuration of a conventional information processing device including such a dedicated processor. As shown in FIG. 11, a conventional information processing device 300 includes a main system 304 configured mainly of a CPU 304a and a subsystem 306 configured mainly of a sub-processor 306a, which is a dedicated processor such as a GPU or a codec. The main system 304 is connected to a main memory 308, and the CPU 304a accesses a main memory 308 via a main system bus 304b and a memory controller 304c. The subsystem 306 is connected to a sub memory 310 dedicated for the subsystem 306, and the sub-processor 306a accesses a sub memory 310 via a subsystem bus 306b and a memory controller 306c. A bus bridge (not shown) is provided between the main system bus 304b and the subsystem bus 306b. 